1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device requiring an initialization operation.
2. Description of the Related Art
A semiconductor device generally includes a fuse circuit to store various pieces of information for setting its operation environment. For example, fuse circuits store redundancy information according to defects, trimming information of internal voltages, Mode Register Set (MRS) information, and so on.
Fuse circuits are divided into physical fuse circuits, whose connection states are controlled by laser radiation, and electrical fuse circuits, whose connection states are controlled by electrical signals.
Recently, electrical fuse circuits, which may be programmed after the package stage, are widely used instead of physical fuse circuits, which are only programmable before the package stage.
During a boot-up mode, the fuse circuit outputs fuse signals, which represent whether fuses are connected and are stored in a predetermined latch circuit. The latch circuit needs an initialization operation during an initialization mode for stable operation of the semiconductor device.
FIG. 1 is a block diagram illustrating a semiconductor device according to a prior art.
Referring to FIG. 1, a semiconductor device 100 includes first to eighth banks 110A to 110H for storing and providing data, first to eighth latch blocks 120A to 120H corresponding to the first to eighth banks 110A to 110H, and a fuse block 130 for outputting first to eighth fuse signals FZDATA0<0:n> to FZDATA7<0:n>, respectively, to the first to eighth latch blocks 120A to 120H during a boot-up mode.
The first to eighth banks 110A to 110H store data inputted from an external device during a write mode, and provide the external device with the stored data during a read mode.
The first to eighth latch blocks 120A to 120H are initialized in response to an initialization signal FZLATRSTB enabled during a predetermined section of an initialization mode, and latch the first to eighth fuse signals FZDATA0<0:n> to FZDATA7<0:n> outputted from the fuse block 130 during the boot-up mode.
The fuse block 130 groups and sequentially outputs the first to eighth fuse signals FZDATA0<0:n> to FZDATA7<0:n> in response to a boot-up mode signal FZYEN enabled during the boot-up mode, and first to fourth bank selection signals FZ_XBK<0:3> sequentially enabled during the boot-up mode. For example, the fuse block 130 groups and simultaneously outputs a pair of the first and fifth fuse signals FZDATA0<0:n> and FZDATA4<0:n>, a pair of the second and sixth fuse signals FZDATA1<0:n> and FZDATA5<0:n>, a pair of the third and seventh fuse signals FZDATA2<0:n> and FZDATA6<0:n>, and a pair of the fourth and eighth fuse signals FZDATA3<0:n> and FZDATA7<0:n> during the boot-up mode.
FIG. 2 is a circuit diagram illustrating the first latch block 120A shown in FIG. 1.
Referring to FIG. 2, the first latch block 120A includes a plurality of latch portions 120A_1 to 120A_n, which are simultaneously initialized in response to the initialization signal FZLATRSTB during the initialization mode and latch the first fuse signals FZDATA0<0:n> during the boot-up mode.
Each of the latch portions 120A_1 to 120A_n includes an initialization unit, a load unit, a latch unit, and an output unit.
The initialization unit initializes a logic level of a first latch node to a logic high level in response to the initialization signal FZLATRSTB.
The load unit transitions the logic high level of the first latch node to a logic low level in response to a first fuse signal FZDATA0<#>.
The latch unit inverts the logic level of the first latch node, and outputs the inverted logic level of the first latch node to a second latch node, and then latches the logic levels of the first and second latch nodes.
The output unit outputs the logic level of the second latch node as a first fuse output signal FZOUT0<#>.
For example, the initialization unit includes a PMOS transistor, to a gate of which the initialization signal FZLATRSTB is inputted, and which is coupled with a high voltage, e.g., a power source voltage VDD, and the first latch node at its source and drain.
The load unit includes an NMOS transistor, to a gate of which the first fuse signal FZDATA0<#> is inputted, and which is coupled with a low voltage, e.g., a ground voltage VSS, and the first latch node at its source and drain.
The latch unit includes a first inverter, input and output nodes which are respectively the first and second latch nodes, and a second inverter, input and output nodes which are respectively the second and first latch nodes.
The output unit includes first and second inverters serially coupled with each other.
The second to eighth latch blocks 120B to 120H have the same structure as the first latch block 120A. However, the second latch block 120B receives the second fuse signals FZDATA1<0:n> instead of the first fuse signals FZDATA0<0:n>, and the third latch block 120C receives the third fuse signals FZDATA2<0:n> instead of the first fuse signals FZDATA0<0:n>, and the fourth lath block 120D receives the fourth fuse signals FZDATA3<0:n> instead of the first fuse signals FZDATA0<0:n>, and the fifth latch block 120E receives the fifth fuse signals FZDATA4<0:n> instead of the first fuse signals FZDATA0<0:n>, and the sixth latch block 120F receives the sixth fuse signals FZDATA5<0:n> instead of the first fuse signals FZDATA0<0:n>, and the seventh latch block 120G receives the seventh fuse signals FZDATA6<0:n> instead of the first fuse signals FZDATA0<0:n>, and the eighth latch block 120H receives the eighth fuse signals FZDATA7<0:n> instead of the first fuse signals FZDATA0<0:n>.
An operation of the semiconductor device 100 is described hereafter.
When the semiconductor device 100 enters the initialization mode, the first to eighth latch blocks 120A to 120H are simultaneously initialized in response to the initialization signal FZLATRSTB, which is enabled during a predetermined section.
Under the condition, when the semiconductor device 100 enters the boot-up mode, the fuse block 130 groups and sequentially outputs the first to eighth fuse signals FZDATA0<0:n> to FZDATA7<0:n> in response to the first to fourth bank selection signals FZ_XBK<0:3>. For example, the fuse block 130 groups and simultaneously outputs a pair of the first and fifth fuse signals FZDATA0<0:n> and FZDATA4<0:n>, and then a pair of the second and sixth fuse signals FZDATA1<0:n> and FZDATA5<0:n>, and subsequently a pair of the third and seventh fuse signals FZDATA2<0:n> and FZDATA6<0:n>, and lastly a pair of the fourth and eighth fuse signals FZDATA3<0:n> and FZDATA7<0:n> during the boot-up mode.
The first to eighth latch blocks 120A to 120H latch the first to eighth fuse signals FZDATA0<0:n> to FZDATA7<0:n>, which are grouped and sequentially inputted.
However, the semiconductor device 100 according to the prior art has the following problems.
The first to eighth latch blocks 120A to 120H include latch portions for each of the first to eighth fuse signals FZDATA0<0:n> to FZDATA7<0:n>. As the first to eighth latch blocks 120A to 120H including the numerous latch portions are simultaneously initialized, an over-current occurs in the semiconductor device 100. The over-current causes the first to eighth latch blocks 120A to 120H to abnormally perform an initialization operation, and furthermore, inevitably causes malfunction of other circuits operating in the initialization mode as well.